1. Field of the Invention
The present invention relates to output buffers. More specifically, the present invention relates to techniques for improving the operation of output buffers.
While the present invention is described herein with reference to illustrative embodiments for particular applications, it should be understood that the invention is not limited thereto. Those having ordinary skill in the art and access to the teachings provided herein will recognize additional modifications, applications, and embodiments within the scope thereof and additional fields in which the present invention would be of significant utility.
2. Description of the Related Art
Output buffers are well known in the art. Output buffers serve to drive loads on memories, logic circuits, output pads and interfaces between internal circuits and output busses. Output buffers are particularly useful in driving heavy capacitive loads. For this purpose, heavy capacitive loads are loads in excess of 30 picofarads.
Conventional buffers are implemented in CMOS technology and are designed to drive the load from its lowest level to its highest level (rail-to-rail). In the case of the capacitive load, this involves a full level charging and discharging of the load between the highest and lowest voltage levels thereof. This causes voltage spikes in the output data and power rails. Such noise affects DC level detection and causes errors and circuit malfunction.
In addition, the requirement that the buffer fully charge and discharge the load significantly slows the operation of the system.
Thus, there is a need in the art to improve the performance of output buffers used to drive capacitive loads.